Master 2014 2015
Stages de la spécialité SAR
Understanding and Optimizing Memory load in Real-time applications


Site :Trac-Nouveau stage
Lieu :LIP6
Encadrant : Sopena Julien
Dates :01/03/2015 au 31/08/2015
Mots-clés : Master SAR, autre qu’ATIAM


Description

Complex embedded systems today commonly involve a mix of real-time and best-effort applications. The recent emergence of small low-cost commodity multicore processors raises the possibility of running both kinds of applications on a single machine, with virtualization ensuring that the best-effort applications cannot steal CPU cycles from the real-time applications. Nevertheless, memory pressure can introduce other sources of delay, that can lead to missed deadlines.

We have recently developed a combined offline/online memory bandwidth monitoring approach to estimate the impact of the memory pressure incurred by the best-effort applications on the execution time of the real-time application. Our approach is compatible with the hardware counters provided by current small commodity multicore processors. Our approach allows the system designer to limit the overhead on the real-time application to under 5% of its expected execution time, while still enabling progress of the best-effort applications.

The purpose of this Master 2 internship is to investigate what part of the real-time application source code leads to high bandwidth traffic. This knowledge will be then used for two purposes : (i) to improve the scheduling of best effort applications while the real-time application is executing its high demanding portions, (ii) to change the source code or the compilation options of these demanding portions so as to reduce the generated memory traffic.